PLDs are a well-known type of integrated circuit that may be programmed to perform specified logic functions. One type of PLD, the Field Programmable Gate Array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, Input/Output Blocks (IOBs), Configurable Logic Blocks (CLBs), dedicated Random Access Memory Blocks (BRAMs), multipliers, Digital Signal Processing blocks (DSPs), processors, clock managers, Delay Lock Loops (DLLs), Multi-Gigabit Transceivers (MGTs) and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by Programmable Interconnect Points (PIPs). The programmable logic implements the logic of a user design using programmable elements that may include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and the programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells during a configuration event that defines how the programmable elements are configured. The configuration data may be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these PLDs, the functionality of the device is controlled by configuration data bits provided to the device for that purpose. The configuration data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell. Static random access memory (SRAM) is an exemplary memory device that is commonly used to store the configuration data bits. The contents of SRAM, however, is lost whenever operational power is removed. As such, operational power is required at all times to maintain the contents of the SRAM intact.
Some PLDs, such as the Xilinx Virtex® FPGA, can be programmed to incorporate blocks with pre-designed functionalities, i.e., “cores”. A core can include a predetermined set of configuration data bits that program the FPGA to perform one or more functions. Alternatively, a core can include source code or schematics that describe the logic and connectivity of a design. Typical cores can provide, but are not limited to, DSP functions, memories, storage elements, and math functions. Some cores include an optimally floor planned layout targeted to a specific family of FPGAs. Cores can also be parameterizable, i.e., allowing the user to enter parameters to activate or change certain core functionality.
Generally, one or more power supplies are often utilized to provide operational power to one or more regions within the PLD. For example, a first power supply may be utilized to provide operational power to core logic within the PLD, such as CLBs and BRAMS, while a second power supply may be used to provide operational power to IOBs, DSPs, memory cells, and other higher voltage circuitry within the PLD. Other power supplies may also be used as necessary depending upon the application.
For example, FIG. 1 exemplifies PLD 100, whereby two power supplies, e.g., VCCAUX and VCCINT, are utilized. Upon power-up of PLD 100, power-on reset (POR) circuit 114 deasserts the control terminal of p-type metal oxide semiconductor (PMOS) transistor 106 to logic a low value, which causes PMOS transistor 106 to transition to a conductive state. The conductive state of PMOS transistor 106 allows current to flow from VCCINT to node 110, thereby charging node 110 to a voltage magnitude that is substantially equal to VCCINT during the power-up sequence.
Once node 110 has reached an acceptable voltage magnitude, e.g., acceptable for initializing PLD circuits 108, POR circuit 114 asserts the control terminal of PMOS transistor 106 to a logic high value, which renders PMOS transistor 106 non-conductive, so as to isolate VCCINT from node 110. Operational amplifier 102 then becomes operational and regulates the voltage magnitude at node 110 using VCCAUX by adjusting the gate voltage of PMOS transistor 104 until node 110 achieves a voltage magnitude that is substantially equal to VREF. As can be seen, however, device 100 does not exhibit a low-power, or suspend mode of operation, since all components of PLD 100, except PMOS transistor 106, remain active once the power-up sequence is complete.
Some FPGAs, therefore, may be configured to provide the lowest possible standby power, i.e., during a suspend mode of operation, which minimizes the amount of operational power that is consumed. In particular, after the PLD enters the suspend mode, all non-essential PLD functions are shut down to minimize power dissipation. All writable clocked elements are write protected against spurious write operations and all PLD inputs and outputs are shut down, which allows the application state of the PLD to be held static during suspend mode. Operational power is, however, maintained to critical circuits within the PLD, such as the SRAM configuration memory, so as to preserve the configured state of the PLD during the suspend mode.
Turning to FIG. 2, for example, an exemplary embodiment of PLD 200 is illustrated, in which a low-power operation during the suspend mode is facilitated. Operation of PLD 200 during normal operation, i.e., the awake mode, is such that signal SUSPEND is deasserted to a logic low level. In response, suspend circuit 216 deasserts signal DISABLE and asserts signal POWER DOWN, which renders transistor 210 non-conductive. In response, operational amplifier 202, in combination with transistor 204, regulates the voltage magnitude at node 212 to be substantially equal to VREF to supply operational power to PLD circuits 214.
The operation of well bias circuit 208 is discussed in U.S. patent Ser. No. 11/252,504 filed on Oct. 18, 2005 by Narasimhan Vasudevan and is incorporated herein by reference in its entirety. Generally, well bias circuit 208 maintains the well potential of transistors 204 and 210 at a voltage magnitude that prevents inadvertent forward biasing of the body diodes that exist within transistors 204 and 210. During the awake mode, for example, the voltage magnitude, VB1, is applied to the well region of transistor 204 by well bias circuit 208 and is substantially equal to VCCAUX. Similarly, the voltage magnitude, VB2, is applied to the well region of transistor 210 by well bias circuit 208 and is substantially equal to the voltage magnitude at node 212. As such, inadvertent forward biasing of the body diodes within transistors 204 and 210 is substantially prevented.
The suspend mode of operation is entered by asserting signal SUSPEND, which causes suspend circuit 216 to assert signal DISABLE. In response, the voltage magnitude at the output of operational amplifier 202 is substantially equal to VCCAUX, which renders transistor 204 non-conductive. In addition, suspend circuit 216 deasserts signal POWER DOWN, which causes transistor 210 to enter a conductive state. In response, the voltage magnitude at node 212 is substantially equal to VCCINT by operation of transistor 210. PLD circuits 214 then derive operational power from VCCINT, which is at a lower voltage magnitude than VREF. In one embodiment, PLD circuits 214 are composed of static random access memory (SRAM), which provides the configuration memory for PLD 200. The leakage current of SRAM decreases exponentially with decreasing supply voltage. Thus, the amount of power consumed by the SRAM during the suspend mode is reduced considerably because the voltage magnitude of VCCINT is generally lower than the voltage magnitude of VREF. Thus, operational power is further reduced even while conserving the configuration memory of PLD 200 during the suspend mode.
As can be verified from FIG. 2, however, deactivation of power supply VCCAUX or VCCINT causes a low-impedance current path to exist. For example, if power supply VCCAUX is deactivated during the SUSPEND mode of operation, then a low-impedance current path exists from VCCINT through transistor 210, node 212 and transistor 204. The current path exists because the body diode of transistor 204 is forward biased due to the voltage magnitude of the drain terminal of transistor 204 being at a higher potential, e.g., VCCINT, than the voltage magnitude of the well region of transistor 204, e.g., ground potential, due to the deactivated power supply VCCAUX. In addition, the voltage magnitude at the control terminal of transistor 204 is also substantially zero due to the disablement of VCCAUX, which renders transistor 204 conductive to create a low-impedance current path between VCCAUX and VCCINT.
If power supply VCCINT is deactivated during the awake mode of operation, on the other hand, then a low-impedance current path exists from VCCAUX through transistor 204, node 212 and transistor 210. The current path exists because the body diode of transistor 210 is forward biased due to the voltage magnitude of the drain terminal of transistor 210 being at a higher potential, e.g., VREF, than the voltage magnitude of the well region of transistor 210, e.g., ground potential, due to the deactivated power supply VCCINT. In addition, the voltage magnitude at the control terminal of transistor 210 could be substantially equal to zero, which renders transistor 210 conductive to create a low-impedance current path between VCCAUX and VCCINT.
Turning to FIG. 3, an alternate embodiment of PLD 300 is illustrated, in which a low-power operation during the suspend mode is facilitated, whereby activation of VCCINT during the suspend mode occurs in response to sensing the voltage magnitude output of operational amplifier 302 after a time delay. In particular, once signal SUSPEND is asserted, signal DISABLE is also asserted within suspend circuit 316 to deactivate operational amplifier 302. Once deactivated, the output voltage magnitude of operational amplifier 302 at node 304 is substantially equal to VCCAUX, which causes transistors 306 and 318 to enter a non-conductive state. Once transistor 318 is rendered non-conductive and after delay 322, transistor 320 is rendered conductive to deassert signal SENSE to a logic low level. In response, transistor 310 is rendered conductive to allow PLD circuits 314 to derive operational power from power supply VCCINT via node 312 during the suspend mode.
The PLD of FIG. 3, however, causes low-impedance current paths to exist during the deactivation of power supply VCCAUX or VCCINT for similar reasons as discussed above in relation to FIG. 2. Efforts continue, therefore, to provide means to prevent current flow through the low-impedance current paths that are created when one or more power supplies are deactivated during the suspend or awake modes of operation.